There are 4 main dopants B, P, Sb and As for CZ Si. Common resistivity ranges are:

Dopant:	Resistivity:	Chart:
Boron:	0.001-140 Ώ cm
Phosphorus:	0.03-140 Ώ
Antimony:	0.008-0.600 Ώ cm
Arsenic:	0.001-0.005 Ώ cm
	0.001-0.004 Ώ cm
	0.002-0.003 Ώ cm

There are 2 main dopants B, P for FZ Si. Common resistivity ranges are:

Dopant:	Resistivity:	Chart:
Boron:	0.2-10000+ Ώ cm
Phosphorus:	0.01-10000+ Ώ cm

The Si wafer surface roughness is guaranteed by repetition of the chemical-mechanical-planarization (CMP) polishing process, not by any measurement, which would be destructive. For the polished side of the wafers the normal roughness value is <0.5nm (<5Å). Any standard Quality Certificate doesn't mention any surface roughness measurements data as the roughness is guaranteed by repetition of the chemical-mechanical-planarization (CMP) polishing process. Common way to measure roughness is with use of Atomic Force Microscope (AFM).
We offer AFM measurements as the service.

NTD FZ stands for Neutron Transmutation Doped Float Zone silicon. NTD is the silicon doping technique. The NTD process takes place when undoped (high purity) mono-silicon rods are irradiated in a thermal neutron flux inside nuclear reactor. The thermal neutron is captured by the 30Si atom, which has a 3% abundance in pure Si. Due to the high neutron/proton ratio of 31Si, it will release a beta and, by converting a neutron to a proton, the Si-31 atom transmutes to a P-31 atom according to this reaction:

30Si + n → 31Si → (β-) 31P.

In the result Phosphorus (n-type) doped silicon, with the lowest resistivity variation of any crystalline silicon product on the market is created.

• Thermal Silicon Oxide is SiO₂ grown by oxidizing the silicon of the wafer itself. This form a hard and dense SiO₂ that is essentially monocrystalline. Thickness range is wide: from 100Å to 50000Å
• Low Temperature Oxide (LTO) or Chemical Vapor Deposition (CVD) deposited SiO₂ is a soft porous SiO₂, used on silicon wafer back-side to absorb impurities during Epi growth.
• Sputtered SiO₂ form a polycrystalline deposited layer that can be grown as thick as 5 or 10µm.
• Electron Beam Evaporated SiO₂ is glass-like but is limited to about 2µm of thickness.

Each of these SiO₂ layers, although chemically the same, actually have significantly different physical properties. It is the customer who decides what oxide is needed

Oxygen dissolved in Silicon is measured according to ASTM F-1188 by IR absorption using FTIR. However this measurement only works for Silicon with resistivity > 0.1 Ohmcm. At lower resistivities IR absorption is too high to get a meaningful measurement. For low resistivity wafers, oxygen content is reported as measured on higher resistivity Silicon made under the same conditions. For critical applications SIMS measurement method is required to mesure bulk oxygen content. However, we can say that for typical Czochralski process expected oxygen content is within 24-38 ppma (ASTM F121-76) limits.

Examples of controlled Oxygen groups:

• O₂ from 31.0 to 36.8 ppma (<111> orientation)
• O₂ from 28.0 to 32.0 ppma (<100> orientation)
• O₂ from 29.0 to 35.0 ppma (<100> orientation)

If Low Oxygen content is critical for your application then we recommend using FZ crystallized Silicon. Then FZ silicon Oxygen content is < 1ppma.

Undoped GaP conductivity type is 'n', which is different to silicon. Intrinsic Si type remain unknown for undoped (can be 'p', can be 'n').

Resistivity, Charge Carrier Concentration and Mobility are related, as follows:

Ro=1/(k × Nc × u)
where Ro is resistivity in Ohm cm
k is charge of a Charge Carrier in Coulombs per Charge Carrier {Charge of an electron}
Nc is Number of Charge Carriers per cm³
u is Charge Carrier Mobility in cm² per Volt Sec

You can check the units
Ro = [Ohm×cm] = [Volt/(Ampere×cm)] = [Volt/(Coulombs/Sec)×cm]  = [(Volt×Sec×cm)/Coulomb]
k = [Coulomb/Atom] {One Dopant atom contributes one electron or hole charge carrier}
Nc = [Dopant Atoms/cm³]
u = [cm²/(Volt×Sec)]

k = 1.602E-19 Coulombs (Charge of an electron - a constant of nature)

The table below gives dependance between concentration and mobility for III-V Compound Semiconductors:

Notes:

• InSb parameters measured at 77K, all others at 300K
• Undoped GaAs:- is normally Semi-Insulating, ultra-pure GaP is Semi-Insulating, none of the others are
• Mobility is that of Majority Charge Carriers; p-type Mobility is Hole Mobility, all others are Electron Mobility

To recalculate from Sheet Resistance in [Ohms/square] to Resistivity [Ohm-cm] the Rs=Ro/t formula is used
where:
t is wafer thickness,
Rs is sheet resistance Ohms/square,
Ro is resistivity in Ohm-cm.

An "Epi-ready" surface is one that was polished and cleaned to be free of microscopic particles, such that an Epi layer can be grown on the surface. Even if the wafers deliveried are certified to be 'epi-ready' it is good industry practise to clean the wafers just before processing.

SEMI refers to the SEMI Organization (https://www.semi.org/) which specifies the standards for silicon wafers and other semiconductor materials. "Prime" and "Semi Prime" wafers are equivalent and the highest grade of a silicon wafer. SEMI organization indicates the bulk, surface and physical properties required to label silicon wafers as "Prime Wafers". "Test" or "Semi Test" wafers are virgin silicon wafers of lower quality than Prime and used primarily for testing processes. SEMI organization indicates the bulk, surface, and physical properties required to label silicon wafers as "Test Wafers". Unlike "Primes" the "Test" wafers may show some surface defects (like scratches, LPDs or particles) or bulk defects (like excessive EPD or impurities).

• All prices are in US Dollars.

• All prices are rounded to the tenths of Dollar.

• Shipping costs and customs fees are not included into material prices.

• Selling full boxes of wafers is preferred. If smaller quantity (below full box) is needed the clean room repacking fee is applied and included into the wafers price. The price is recalculated accordingly.

• The repacking fee for silicon wafers with 8" diameter is higher than regular repacking fee.

In stock Si wafers have no minimum order quantity (no MOQ) and we are happy to deliver just one wafer. However, we apply a clean room repacking fee for each box we have to repack. The split cassette fee is $150/box for all diameters below Ø8" (<200mm) and $250/box for Ø8" (=200mm). We do not repack Ø12" (=300mm) and any larger diameter wafers.

We also offer made-to-order Si wafers and specialize in small quantities. The MOQ for made-to-order depends on the specifications (please click) that we shall agree before offering.

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